1. Technical Field
The present invention relates to physical unclonable functions, and more particularly, to on-chip physical unclonable function generation and management thereof.
2. Description of the Related Art
Process variations of integrated circuits present a fundamental reliability challenge with regard to generation and measurement of physical unclonable functions. In particular, there is an inherent contradiction between forming a physical unclonable function (PUF) which depends on large variability and fabricating a reliable PUF measurement system which depends on low variability while integrating both functions monolithically on the same chip. For example, although process variability maximizes the effectiveness of a PUF, process variability degrades the performance of the measurement circuit. As such, a manufacturing design goal is to maximize process variability for the PUF (σPUF) circuit and minimize process variability for the measurement circuit. In addition, process, voltage supply, temperature, and aging variability results in measurement incertitude that forms an incertitude zone defined by a measurement standard deviation (σmeas).
For example, diagram 100 of FIG. 1 illustrates an example of a voltage normal distribution due to process variability for a PUF and its binarization by a perfect measurement system. As illustrated in diagram 200 of FIG. 2, measurement error results in an incertitude zone 202 that stems from process variability. Although the measurement error cannot be reduced to zero, any PUF scheme should incorporate a measurement system that minimizes measurement variability. However, this is difficult to achieve when the PUF scheme is implemented on-chip due to the conflicting goals of maximizing process variability for PUF generation and minimizing process variability to manufacture a reliable integrated circuit.